1. Field of the Invention
The invention relates to the field of MOS buffers.
2. Prior Art
Numerous metal-oxide-semiconductor (MOS) digital buffer circuits are well-known and currently implemented in many MOS integrated circuits. Where these buffer circuits are employed to provide an output signal from an integrated circuit, a relatively large voltage swing is desirable along with high power, and the required speed. In order for these buffer circuits to provide this performance for typical p-channel and n-channel MOS circuits, they consume power when their output is in the high state and in the low state.
Several circuits are used to reduce this consumption of power when the buffer is not in use. In one commercial memory, for example, a clock power supply is employed which removes the power from the output buffer circuits. This most often requires external circuitry since it is difficult to provide "on chip" switching of power supply potentials.
With the invented buffer, a powered down mode without external switching of power supply potentials is obtained. Low threshold (zero threshold) voltage devices are employed to power down the output buffers without substantially effecting the operating performance of the buffer circuits.